1. Field of the Invention
The present invention relates to a process for preparing a semiconductor device and, more specifically, to a process for forming a via-hole in an interlayer dielectric film provided in a multilayered metal wiring.
2. Prior Art
Conventionally, via-holes on a semiconductor substrate which are required to a multilayered metal wiring are formed by a reactive ion etching using, for example, SF.sub.6 gas. In this case, if aluminum or an aluminum alloy is used as a lower layer of the metal wiring (first wiring), the aluminum or aluminum alloy recoils to form deposits (for example, AlF.sub.3 and Al.sub.2 O.sub.3) in the via-hole. These deposits have insulating properties and thus can cause a defective conduction between the first and second wirings. In a conventional manner the deposits have been removed by so-called wet etching method using hydrofluoric acid aqueous solution.
Such a wet etching method, however, may often etch too much interlayer-dielectric material existing around the deposits. Because hydrofluoric acid is hard to penetrate into the interface of the deposits and the interlayer dielectric film, and thus the interlayer-dielectric film material around the deposits must be much more etched than necessary (refer to FIG. 3). Therefore, the via-hole becomes far larger in diameter than optimal.
The present invention is accomplished in view of the abovementioned problem, and an object thereof is to provide a process for preparing a semiconductor device which is formed with via-holes such as to have an optimal diameter for assuring electrical characteristics thereof.